Field programmable gate arrays implementation of two-point non-uniformity correction and bad pixel replacement algorithms

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dc.authorscopusid57223924218
dc.authorscopusid57223922820
dc.authorscopusid36793379200
dc.authorscopusid57204335036
dc.authorscopusid55666247200
dc.contributor.authorNjuguna, J.C.
dc.contributor.authorAlabay, E.
dc.contributor.authorÇelebi, A.
dc.contributor.authorÇelebi, A.
dc.contributor.authorGüllü, Mehmet Kemal
dc.date.accessioned2022-02-15T16:58:11Z
dc.date.available2022-02-15T16:58:11Z
dc.date.issued2021
dc.departmentBakırçay Üniversitesien_US
dc.descriptionKocaeli University;Kocaeli University Technoparken_US
dc.description2021 International Conference on INnovations in Intelligent SysTems and Applications, INISTA 2021 -- 25 August 2021 through 27 August 2021 -- -- 172175en_US
dc.description.abstractIn this paper, the hardware architecture for two-point non-uniformity correction (TPNUC) and bad pixel replacement (BPR) algorithms are presented based on field-programmable gate arrays (FPGA) for infrared focal plane arrays (IRFPA). An efficient hardware architecture modeled using C++ in the High-Level Synthesis (HLS) tool is presented. The design is tested on an FPGA fabricated at a 16 nm technology node. The design achieves a maximum frequency of 300 MHz and one pixel per clock. A thermal camera development platform (FullScale USB3A) with a resolution of 640×480 is used as the source for the raw video. The simulation results from MATLAB and FPGA posed close similarities. © 2021 IEEE.en_US
dc.identifier.doi10.1109/INISTA52262.2021.9548499
dc.identifier.isbn9781665436038
dc.identifier.scopus2-s2.0-85116703354en_US
dc.identifier.scopusqualityN/Aen_US
dc.identifier.urihttps://doi.org/10.1109/INISTA52262.2021.9548499
dc.identifier.urihttps://hdl.handle.net/20.500.14034/362
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.relation.journal2021 International Conference on INnovations in Intelligent SysTems and Applications, INISTA 2021 - Proceedingsen_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectBad pixel replacementen_US
dc.subjectFixed pattern noiseen_US
dc.subjectFPGAen_US
dc.subjectHLSen_US
dc.subjectIRFPAen_US
dc.subjectTwo-point non-uniformity correctionen_US
dc.subjectC++ (programming language)en_US
dc.subjectHigh level synthesisen_US
dc.subjectIntegrated circuit designen_US
dc.subjectLogic gatesen_US
dc.subjectMATLABen_US
dc.subjectPixelsen_US
dc.subjectBad pixel replacementen_US
dc.subjectField-programmable gate array implementationsen_US
dc.subjectFixed-pattern-noiseen_US
dc.subjectHardware architectureen_US
dc.subjectHigh-level synthesisen_US
dc.subjectNonuniformity correctionen_US
dc.subjectReplacement algorithmen_US
dc.subjectSynthesis toolen_US
dc.subjectTwo-pointen_US
dc.subjectTwo-point non-uniformity correctionen_US
dc.subjectField programmable gate arrays (FPGA)en_US
dc.titleField programmable gate arrays implementation of two-point non-uniformity correction and bad pixel replacement algorithmsen_US
dc.typeConference Objecten_US

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