Field programmable gate arrays implementation of two-point non-uniformity correction and bad pixel replacement algorithms
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Tarih
2021
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
Institute of Electrical and Electronics Engineers Inc.
Erişim Hakkı
info:eu-repo/semantics/closedAccess
Özet
In this paper, the hardware architecture for two-point non-uniformity correction (TPNUC) and bad pixel replacement (BPR) algorithms are presented based on field-programmable gate arrays (FPGA) for infrared focal plane arrays (IRFPA). An efficient hardware architecture modeled using C++ in the High-Level Synthesis (HLS) tool is presented. The design is tested on an FPGA fabricated at a 16 nm technology node. The design achieves a maximum frequency of 300 MHz and one pixel per clock. A thermal camera development platform (FullScale USB3A) with a resolution of 640×480 is used as the source for the raw video. The simulation results from MATLAB and FPGA posed close similarities. © 2021 IEEE.
Açıklama
Kocaeli University;Kocaeli University Technopark
2021 International Conference on INnovations in Intelligent SysTems and Applications, INISTA 2021 -- 25 August 2021 through 27 August 2021 -- -- 172175
2021 International Conference on INnovations in Intelligent SysTems and Applications, INISTA 2021 -- 25 August 2021 through 27 August 2021 -- -- 172175
Anahtar Kelimeler
Bad pixel replacement, Fixed pattern noise, FPGA, HLS, IRFPA, Two-point non-uniformity correction, C++ (programming language), High level synthesis, Integrated circuit design, Logic gates, MATLAB, Pixels, Bad pixel replacement, Field-programmable gate array implementations, Fixed-pattern-noise, Hardware architecture, High-level synthesis, Nonuniformity correction, Replacement algorithm, Synthesis tool, Two-point, Two-point non-uniformity correction, Field programmable gate arrays (FPGA)
