An FPGA based Real-Time Flat Field Correction for Infrared Focal Plane Arrays

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dc.authorscopusid57223924218
dc.authorscopusid57223922820
dc.authorscopusid36793379200
dc.authorscopusid57904162400
dc.authorscopusid55666247200
dc.contributor.authorNjuguna J.C.
dc.contributor.authorAlabay E.
dc.contributor.authorCelebi A.
dc.contributor.authorCelebi A.T.
dc.contributor.authorGullu M.K.
dc.date.accessioned2024-03-09T19:39:55Z
dc.date.available2024-03-09T19:39:55Z
dc.date.issued2023
dc.departmentİzmir Bakırçay Üniversitesien_US
dc.description2023 Innovations in Intelligent Systems and Applications Conference, ASYU 2023 -- 11 October 2023 through 13 October 2023 -- -- 194153en_US
dc.description.abstractCorrection of fixed pattern noise (FPN) plays a vital role in fully exploiting the potential of the infrared focal plane arrays (IRFPA). The paper presents FPGA based hardware architecture for flat field correction (FFC) for thermal camera with an external shutter. The proposed hardware architecture is built using a high-level synthesis (HLS) approach to generate Verilog or VHDL codes from C++ code. HLS Video Direct Memory Access (VDMA) generated have 256-bit width interconnected with First In First Out (FIFO) that reduces Double Data Rate (DDR) traffic. The design is tested on Efinix quantum technology that delivers substantial power, performance, area, and advantages over traditional FPGA products. The design achieves a maximum frequency of 400 MHz and one pixel per clock. Long Wavelength Infrared (LWIR) thermal camera with a resolution of $640\times 512$ and 12um pitch is used as the source for the raw video. The design achieves 60 frames per second (fps). © 2023 IEEE.en_US
dc.description.sponsorshipAuthors would like to thank KuanTek Electronics and Information Technology Company for providing hardware and software infrastructure to conduct this research.en_US
dc.identifier.doi10.1109/ASYU58738.2023.10296698
dc.identifier.isbn9798350306590
dc.identifier.scopus2-s2.0-85178256949en_US
dc.identifier.scopusqualityN/Aen_US
dc.identifier.urihttps://doi.org/10.1109/ASYU58738.2023.10296698
dc.identifier.urihttps://hdl.handle.net/20.500.14034/1542
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.relation.ispartof2023 Innovations in Intelligent Systems and Applications Conference, ASYU 2023en_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectAXI4; AXI4-STREAM; FFC; FPA; FPGA; FPN; HLS; IRFPA; LWIR; RISC-V; TPNUCen_US
dc.subjectC++ (programming language); Cameras; Codes (symbols); Computer hardware description languages; Field programmable gate arrays (FPGA); Focal plane arrays; Focusing; Infrared devices; Infrared radiation; Integrated circuit design; Memory architecture; AXI4; AXI4-STREAM; Fixed-pattern-noise; Flat field correction; Focal-plane arrays; FPA; High-level synthesis; Infrared focal plane array; Infrared focal planes; Long-wavelength infrared; RISC-V; TPNUC; High level synthesisen_US
dc.titleAn FPGA based Real-Time Flat Field Correction for Infrared Focal Plane Arraysen_US
dc.typeConference Objecten_US

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