Njuguna J.C.Alabay E.Celebi A.Celebi A.T.Gullu M.K.2023-03-222023-03-2220229781665450928https://doi.org/10.1109/SIU55565.2022.9864768https://hdl.handle.net/20.500.14034/879This paper presents a novel hardware architecture for the minimum output sum of squared error (MOSSE) tracker algorithm. The proposed hardware architecture is built using a high-level synthesis (HLS) approach to generate hardware blocks from C++ code. Furthermore, real-time testing and verification are done using an FPGA device fabricated at a 16nm technology node. The microbolometer thermal imaging sensor which has 17 ?m pixel pitch, 640×480 video resolution and 30 frames/second (fps) frame rate is used. Using the HLS tool, the maximum clock frequency and frame rate of 300 MHz and 60 fps are achieved respectively. Generated register transfer level (RTL) and Matlab simulations pose negligible differences between hardware and software implementations. Experimental results reveal that the proposed architecture balances hardware resource utilization and target tracking accuracy for consumer electronics applications. © 2022 IEEE.eninfo:eu-repo/semantics/closedAccessFPGAhardware architectureHLSMOSSE trackerC++ (programming language)High level synthesisInfrared imagingMATLABTarget trackingC++ codesFrame-rateHardware architectureHardware blocksHardware implementationsHigh-level synthesisMinimum output sum of squared error trackerNovel hardwareReal-time object trackingSum of squared errorsField programmable gate arrays (FPGA)Conference Object10.1109/SIU55565.2022.9864768WOS:0013071634001072-s2.0-85138730368N/A