Njuguna, J.C.Alabay, E.Çelebi, A.Çelebi, A.Güllü, Mehmet Kemal2022-02-152022-02-1520219781665436038https://doi.org/10.1109/INISTA52262.2021.9548499https://hdl.handle.net/20.500.14034/362Kocaeli University;Kocaeli University Technopark2021 International Conference on INnovations in Intelligent SysTems and Applications, INISTA 2021 -- 25 August 2021 through 27 August 2021 -- -- 172175In this paper, the hardware architecture for two-point non-uniformity correction (TPNUC) and bad pixel replacement (BPR) algorithms are presented based on field-programmable gate arrays (FPGA) for infrared focal plane arrays (IRFPA). An efficient hardware architecture modeled using C++ in the High-Level Synthesis (HLS) tool is presented. The design is tested on an FPGA fabricated at a 16 nm technology node. The design achieves a maximum frequency of 300 MHz and one pixel per clock. A thermal camera development platform (FullScale USB3A) with a resolution of 640×480 is used as the source for the raw video. The simulation results from MATLAB and FPGA posed close similarities. © 2021 IEEE.eninfo:eu-repo/semantics/closedAccessBad pixel replacementFixed pattern noiseFPGAHLSIRFPATwo-point non-uniformity correctionC++ (programming language)High level synthesisIntegrated circuit designLogic gatesMATLABPixelsBad pixel replacementField-programmable gate array implementationsFixed-pattern-noiseHardware architectureHigh-level synthesisNonuniformity correctionReplacement algorithmSynthesis toolTwo-pointTwo-point non-uniformity correctionField programmable gate arrays (FPGA)Conference Object10.1109/INISTA52262.2021.95484992-s2.0-85116703354N/A